1. Field of the Invention
The present invention relates generally to integrated-circuit memory arrays, and in particular, to adjusting read source line coupled to a reference array for capacitance matching with a memory array.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as Electrically Erasable Programmable Read-Only Memory (EEPROM) and flash memory are used in a variety of modern applications. A flash memory is designed with an array of memory cells that can be independently programmed and read. Sense amplifiers in a flash memory are used to determine the data value or values stored in a non-volatile memory. In a typical sensing scheme, an electrical current through the memory cell being sensed is compared to a reference current by a current sense amplifier.
A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
NROM devices use a relatively thick bottom oxide, e.g. greater than 3 nanometers, and typically about 5 to 9 nanometers, to prevent charge loss. Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell. However, the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell. Moreover, the erase time must be increased gradually during program and erase cycling due to the hard-to-erase accumulation of charge in the charge trapping structure. This accumulation of charge occurs because the hole injection point and electron injection point do not coincide with each other, and some electrons remain after the erase pulse. In addition, during the sector erase of an NROM flash memory device, the erase speed for each cell is different because of process variations (such as channel length variation). This difference in erase speed results in a large Vt distribution of the erase state, where some of the cells become hard to erase and some of them are over-erased. Thus the target threshold Vt window is closed after many program and erase cycles and poor endurance is observed. This phenomenon will become more serious as the technology keeps scaling down.
A typical flash memory cell structure positions a tunnel oxide layer between a conducting polysilicon tunnel oxide layer and a crystalline silicon semiconductor substrate. The term “substrate” refers to a source region and a drain region separated by an underlying channel region. A flash memory read can be executed by a drain sensing or a source sensing. For source side sensing, one or more source lines are coupled to source regions of memory cells for reading current from a particular memory cell in a memory array.
FIG. 1 is a block diagram illustrating a conventional source sensing memory circuit 100 with a main memory array 120 coupled to multiple reference mini-arrays 140, 141, 142, 143, 144 and 146 through a Y-pass gate 130 in a non-volatile memory with 1C:1C source side sensing scheme. The 1C:1C ratio denotes a single memory cell in the main memory array 120 as opposed to a single reference cell in a specific reference array. Sixty-four sense amplifiers SA0 110, SA1 111, . . . SA31 112, SA32 113, . . . SA62 114 and SA63 115 are typically required to perform a read operation. Each sense amplifier in the memory circuit 100 is associated with a reference cell in a particular reference mini-array and a source line. The specific connections are described as follows. The sense amplifier 110 receives a first input from a source line 160 connected to a memory cell 121 and a second input from a source line 170 connected to a reference cell 150. The sense amplifier 111 receives a first input from a source line 161 connected to a memory cell 122 and a second input from a source line 171 connected to a reference cell 151. The sense amplifier 112 receives a first input from a source line 162 connected to a memory cell 123 and a second input from a source line 172 connected to a reference cell 152. The sense amplifier 113 receives a first input from a source line 163 connected to a memory cell 124 and a second input from a source line 173 connected to a reference cell 153. The sense amplifier 114 receives a first input from a source line 164 connected to a memory cell 125 and a second input from a source line 174 connected to a reference cell 154. The sense amplifier 115 receives a first input from a source line 165 connected to a memory cell 126 and a second input from a source line 175 connected to a reference cell 155. A shortcoming of the memory circuit 100 is that the layout area will be large because each sense amplifier is associated with a particular reference mini-array and a particular source line coupled to the reference mini-array.
FIG. 2 is a block diagram illustrating another conventional source sensing memory circuit 200 with the main memory array 120 coupled to shared reference mini-arrays 210 and 220 in the non-volatile memory with a 1C:1C source side sensing scheme. Each reference mini-array is shared among thirty-two sense amplifiers by an interconnect conductor bar. The reference mini-array 210 includes a reference cell 211 connected to a reference metal bit line 212, which in turn is connected to an interconnect conductor bar 230, which is in turn connected to a source line 250 and the first thirty-two sense amplifiers, SA0 110, SA1 111, . . . SA31 112. The reference mini-array 220 includes a reference cell 221 connected to a reference metal bit line 222, which is in turn connected to an interconnect bar 240, which in turn is connected to a source line 260 and the next thirty-two sense amplifiers, SA32 113, SA62 114, . . . SA63 115. The interconnect conductor bars 230 and 240 tend to be lengthy, typically longer than 1000 μm. Although the interconnect bars 230 and 240 provide the backbone for sharing a reference mini-array between thirty-two sense amplifiers, the addition of an interconnect bar and one additional metal line for connecting between each sense amplifier and the interconnect conductor bar contribute to an increase in capacitance to a source line coupled to a reference mini-array, producing undesirable capacitance mismatching between source lines in a main memory array cell and a mini-array reference cell, as well as inducing margin loss with a read high Vt or a read low Vt.
Therefore, there is a need for a non-volatile memory that provides source side sensing in which the dimension of the layout area is reduced while compensating for capacitance mismatching arising between source lines of a memory cell in the main memory array and reference cells in a reference mini-array.